The scaling-down of twin Silicon-oxide-nitride-oxide-silicon (SONOS) memory

transistor has been extensively studied and its application to multi-bit/cell Flash device has been also presented. The scaling issues of SONOS memory is generally addressed in terms of both NAND and NOR Flash application. In the case of NAND SONOS Flash, there are some significant process integration issues about selection transistor, contact resistance, gate filling process margin, and dielectric scaling limitations which should be first worked out, even though FinFET structure can be successfully introduced. However, those kinds of difficulties can be readily solved in NOR SONOS Flash devices, since the program and erase of NOR SONOS Flash devices is based on the channel hot electron (CHE) and hot hole (HH) injection mechanisms, respectively. In addition, NOR SONOS Flash can easily extend the memory density without increasing cell area, if multi-bit/cell storage scheme can be adopted. Recent progress on multi-bit SONOS memory, especially 2-bit/cell, has been faced with the spatial charge redistribution problem during or after charge injection. As the scaling-down of multi-bit SONOS device proceeds, the spatial distribution of trapped charges and their transient behavior in a nitride layer are of significance and finally become the scaling limitation of gate length of cell transistor. In order to solve this problem, the twin SONOS memory (TSM) transistor which consists of physically separated SONOS storage nodes has been proposed. It is fabricated through the combination of the damascene gate and newly developed outer sidewall processes. The fabricated 80-nm gate TSM devices show stable 2-bit memory characteristics regardless of device scaling-down and confirm their good reliability in terms of endurance and retention, since they are inherently free from spatial charge distribution. Besides, the device parameters¡¯ optimization process of 80-nm gate TSM device structure has been carried out. Through these experimental works that are controlled by the physically separated distance of storage nodes and their sizing, the usage of halo doping process instead of enhancing blanket channel doping, and the limited main gate oxide thinning each, the optimized parameters can be drawn and eventually the best performance of 80-nm gate 2-bit/cell SONOS transistor which are more competitive and applicable than previous works is presented. Together with parameters¡¯ optimization, the aggressive scaling-down of fabrication process which consists of the damascene gate and very fine poly-Si sidewall processes results in the 62-nm gate twin SONOS memory transistors as well. Its stable 2-bit operation and fairly good reliability characteristics are measured so as to extend the …